Test device and a test method

ABSTRACT

A test device and a test method, the test device comprising a bus controller for the transmission and reception of bus messages, the bus controller having a message memory for offering transmission data for bus messages, the message memory having a memory capacity for a bus message sequence with bus messages to be transmitted within a single transmission cycle or a transmission cycle sequence. The test device includes an intermediate memory for the storage of transmission data for bus messages with a larger storage capacity than the message memory. The test device furthermore comprises a transmission preparing means for reading transmission data from the intermediate memory and for writing, in advance of reading of the bus controller, to the message memory of the bus controller so that the bus message sequence is expanded by additional bus messages which are transmitted by the bus controller within the transmission cycle or the transmission cycle sequence on the motor vehicle bus.

The invention relates to a test device and a test method for a motorvehicle bus, the test device comprising a bus controller for thetransmission and reception of bus messages, the bus controller having amessage memory for offering transmission data for bus messages, themessage memory having a storage capacity for a bus message sequence withbus messages to be transmitted within a single transmission cycle or atransmission cycle sequence.

A typical bus controller for, to take an example, a FlexRay bus has apredetermined storage capacity in its message memory so that busmessages, which are to be transmitted within a bus message sequence onthe motor vehicle bus, fit into the message memory. For example a buscontroller for a FlexRay bus has a predetermined message capacity of forexample approximately 40 to 70 bus messages. The bus messages to betransmitted in a sequence of transmission cycles are ready in themessage memory. The bus controller may however not transmit anyadditional bus message but only those which are able to be stored in themessage memory.

The storage capacity of the message memory is designed for typical tasksof a bus controller. The bus controller constitutes for example acomponent of a control module for the control of brakes, the engine orsome other component of the motor vehicle such as a sensor or anactuator. For such typical control tasks the storage capacity of themessage memory suffices. For analysis and simulation purposes on theother hand a larger memory capacity is required.

When for example a test device is to simulate several control units,actuators and sensors, it must possess a bus controller with for examplea larger message memory capacity. Such bus controllers are however notavailable as standard components. As an alternative it would be possibleto utilize several bus controllers in order to so increase thetransmission capacity. This is however complex.

One object of the present invention is to increase the transmissioncapacity of a bus controller in a test device.

In order to achieve this object in a test device of the type initiallymentioned there is a provision such that it comprises an intermediatememory for the storage of transmission data for bus messages with alarger storage capacity than the message memory and that the test devicehas a transmission preparing means for reading out the transmission datafrom the intermediate memory and for writing, ahead of reading the buscontroller, to the message memory of the bus controller so that the busmessage sequence is expanded by additional bus messages, which aretransmitted by the bus controller within the transmission cycle or thetransmission cycle sequence on the motor vehicle bus. Furthermore theobject is attained by a test method in accordance with the teaching ofthe invention as claimed in a further independent claim.

One principal notion of the invention is that the transmission preparingmeans inserts additional bus messages into the message memory which areto be transmitted within a transmission cycle or a transmission cyclesequence using the motor vehicle bus. The transmission preparing meansfunctions in a manner ahead of the bus controller, i. e. it puts the busmessage to be transmitted is ready in the message memory in good time,which is read by the bus controller.

The term “bus message sequence” may in the context of the invention meanthat only a single bus message can be transmitted. Furthermore the busmessage sequence may also include transmission interruptions, i. e.between the bus messages to be transmitted other bus subscribers maytransmit messages. This is for example the case with a time divisionmultiple access (TDMA) method. When the test device receives busmessages of other bus subscribers, the transmission cycle may be termedthe transmission and reception cycle or transmission and reception cyclesequence.

In accordance with the invention a standardized bus controller, i. e. astandard component, can be employed. The storage capacity of the messagememory does not have to be expanded. For example the bus controller maybe a standardized software or hardware component.

The message memory constitutes a sort of buffer memory. The buscontroller transmits, within a transmission cycle or transmission cyclesequence with several transmission cycles a larger number of busmessages than the storage capacity of its message memory would allow foras such.

The test device may for example be employed as a simulator and simulateseveral bus subscribers.

Preferably the bus controller reads the transmission data sequentiallyfrom the message memory. The transmission preparing means works ahead ofthe readout by the bus controller.

It will be clear that the message memory may be a plain transmissionmemory. It is preferred for the message memory to be a transmission andreception memory, in which the bus messages to be transmitted andreceived as well are stored.

Preferably the transmission preparing means include a head preparingmeans for writing head data to the message memory.

Furthermore the transmission preparing means have a user data preparingmeans for writing user data to the message memory. The head data servefor the production of heads of the bus messages, while the user data areprovided for user data adjoining the message heads. The head preparingmeans operates ahead of the user data preparing means so that the headdata are entered even prior to the start of a locked phase, in which thebus controller blocks writing of message heads to the message memoryprior to the transmission of a respective bus message, but however theuser data can not yet be modified. Accordingly the user data preparingmeans may still modify the user data, whereas the head data of arespective bus message have already been set. Even in this off time thebus controller prepares to transmit the respective bus message.

The head data are preferably provided in the message memory with anindex or a pointer to a memory location, which indicates the respectiveuser data of the bus message to be transmitted.

Admittedly the locked phase could be defined by a time relatedcondition. Preferably however the locked phase is defined by an offnumber of bus messages for which the bus controller blocks the writingof message heads to the message memory. The bus controller for exampleblocks the head data for an off number (which is predetermined) of busmessages, which are to be transmitted following the bus messagecurrently to be transmitted.

The storage capacity of the message memory is provided for a maximumnumber of bus messages dependent on the size of the bus messages. It isclear that in the case of large messages the storage capacity willmerely suffice for less bus messages, while a larger number of smallerbus messages can be accommodated in the message memory.

The bus is preferably a time division multiple access (TDMA) bus.Preferably the bus is a FlexRay bus.

For reception of transmission data to be written to the intermediatememory the test device preferably possesses a control interface for anoperating means, as for example a personal computer. As an applicationprogram the operating means preferably runs a test program, whichcommunicates by way of a control interface where for example it definesthe bus messages to be transmitted and/or the bus message to bereceived.

Preferably the test device is adapted to transmit acknowledging messagesby way of the control interface, the acknowledging messagesacknowledging bus messages transmitted on the motor vehicle bus by thebus controller. Accordingly the test program running on the PC as anexample will indicate whether a bus message to be transmitted has infact been sent. The bus controller for example marks in the messagememory bus messages as “transmitted”, when it has transmitted them onthe bus.

The acknowledgement messages may completely or only partly contain thecontent of the bus messages. as for example the respective head data.

For the reception of bus messages with the aid of a standard buscontroller the following measures are advantageous, which represent aninvention in their own right:

Preferably the bus controller is namely adapted for writing bus messagesof other subscribers to the message memory, which by other bussubscribers are sequence-transmitted after or between bus messages to betransmitted by the bus controller in or outside the bus messages. Theother bus subscribers transmit bus messages for example between therespective bus messages transmitted by the bus controller of the testdevice within the transmission cycle or transmission cycle sequence.

A typical property of standard bus controllers is to receive many busmessages but not to forward them owing to lack of relevance, for examplewhen they fail to contain any user data. In the case of a FlexRay busthey are for example so-called zero frames. For testing it is however anadvantage if such zero frames or other bus messages which are as suchotherwise discarded, are received and for example offered to the controlinterface for the PC. Preferably the test device will for this purposehave a receiving means setting control instructions for the buscontroller to receive bus messages at certain slots of the motor vehiclebus.

The receiving means for example marks slots of the motor vehicle bus forthe respective bus messages to be received in the message memory with areceived mark, the bus controller recognizing on the basis of thereceived mark that it is to write the respective bus message to theslots provided with a received mark.

The respective memory locations are for example associated with thememory locations or slots of the motor vehicle bus. The memory locationswill for example possess a slot mark.

The bus controller will preferably designate those memory locations,which are provided with a received mark, with a zero mark or a “nothingreceived mark”, if at the respective memory location or slot no busmessage has been received. The bus controller best describes thosememory locations having a received mark with a zero information mark,for example a zero frame mark and more especially a frame flag, when therespective bus message for example comprises zero information, i. e. forexample is a zero frame. The receiving means preferably issues the zeromark or “nothing received mark” or the zero information mark to thecontrol interface.

Furthermore on reception preceding or ahead operation within the meaningof the invention is an advantage. The storage capacity of the receptionmemory, which simultaneously may be the transmission memory of the buscontroller, is limited. The receiving means however reads out thereceived bus messages so rapidly and in advance from the message memorythat the respective memory location or slot of the message memory isquickly ready for the writing in of freshly received bus message. Whichbus messages are respectively to be received, is marked by the receivingmeans, as explained above, in the message memory of the bus controller.

It will be apparent that in the message memory only bus message whichare only to be received or only to be transmitted or to be transmittedand received may be stored.

In the following one working example of the invention will be describedwith reference to the accompanying drawings.

FIG. 1 is a diagrammatic view of a test device for testing a bus of amotor vehicle.

FIG. 2 is a diagrammatic showing of a bus message which is transmittedon the motor vehicle bus.

FIG. 3 shows a transmission cycle sequence with two transmission cycles,during which bus messages are transmitted on the motor vehicle bus.

FIG. 4 shows diagrammatic views of a message memory and an intermediatememory of the test device in accordance with FIG. 1.

FIG. 5 shows a still further diagrammatic view of the intermediatememory according to FIG. 4.

A test arrangement 10 includes a test device 11 for connection with amotor vehicle bus 12 of a motor vehicle 13. The motor vehicle bus 12 isa FlexRay bus.

The motor vehicle bus 12 comprises channels 14 a and 14 b. The testdevice 11 can also be termed a bus coupler 15 for an operating means 16.The operating means 16 comprises a PC or personal computer, as forexample a notebook, which is able to be coupled by the bus coupler 15 tothe motor vehicle bus 12.

All in all the test device 10 constitutes a simulation and analyzingtool 18 for simulation of the bus load on the bus 12 or for analysis ofthe bus messages transmitted by way of the bus 12.

Bus subscribers 19 are coupled with the motor vehicle bus 12, whichrespectively each include a bus controller 20. The bus subscribers 19comprise for example an engine control device 21 for the control of anengine 22, a sensor 23 and furthermore an actuator 24 which arerespectively coupled via a bus controller 20 on the motor vehicle bus12. While engine control device 21 for example is coupled with bothchannels 14 a and 14 b, the sensors and actuators 23 and 24 are onlycoupled with respectively one of the channels 14 a and 14 b.

The test device 11 is coupled by way of connection leads 25 with the bus12, i. e. in the present case with the two channels 14 a and 14 b, itbeing possible for the test device 11 to be only coupled with one of thechannels 14 a or 14 b.

The operating means 16 is connected by way of a line 26 with the buscoupler 15. The line 26 is for example coupled with a control interface27 of the test device 11. The operating means 16 comprises a simulationand analysis module 28, i. e. a program, which includes a program codeable to be implemented by a processor 29 of the operating means 16.

The bus subscribers 19 and furthermore the test device 11 transmit busmessages 30 a through 30 k on the bus 12. The bus message 30 a through30 e are bus message of a first transmission cycle 31, whereas the busmessages 30 f through 30 k are components of a second transmission cycle32. The transmission cycles 31 and 32 are components of a transmissioncycle sequence 33.

For the transmission of the bus messages 30 a through 30 e there are theslots 34 a through 34 e of the transmission cycle 31. The bus message 30f through 30 k have the memory locations 35 f through 35 k of thetransmission cycle 32.

The motor vehicle 13 is in a simulation or test stage. For examplefurther, planned bus subscribers 36 are to be coupled with the bus 12,which however are not completely developed and later are to comprise abus controller 20. One task of the test device 11 is to transmit busmessages instead of the planned bus subscribers 36 on the bus 12. Forthis purpose it would be necessary to provide three bus controllers 20in the case of the test device 11, since one storage capacity 48 of themessage memories 37 of the bus controllers 20 would not suffice to storeall bus messages 30 to be transmitted by the planned bus subscribers 36.It is here that the invention provides a remedy.

The test device 11 comprises an intermediate memory 38, which ultimatelyserves to increase the capacity of the message memory 37. Theintermediate memory 38 and the message memory 37 are however mutuallyseparate units.

A communication function 39, as for example a software function, of thetest device 11 receives at the control interface 27 from the simulationand analysis module 28 on the bus 12 bus messages 30 to be transmittedand writes them to the intermediate memory 38.

A transmission preparing means 40 reads from the intermediate memory 38and writes the data therefrom for the bus messages 30 to be transmittedto the message memory 37.

In the receiving means a receiving function 41 is active, which forms areceiving means. The receiving function 41 reads bus messages 30received by the bus controller 20 and written to the message memory 37and writes the content thereof to the intermediate memory 38. Thecommunication function 39 then reads the bus messages 30 received fromthe test device 11 out of the intermediate memory 30 and communicatesthem to the simulation and analysis module 28 of the operating means 16.

Each of the bus messages (30 a through 30 k) comprises a message head 44and user data 45 and a check part 46. The bus messages 30 may alsocomprise further information, as for example time information or thelike.

The task of the bus controller 20 s to manage communication on the motorvehicle bus 12. Same comprises for example the generation of check parts46, a time synchronization with the respective other bus subscribers 19and 36 or the like.

The planned bus subscribers 36, which are simulated by the test device11, are for example to transmit the bus messages 30 a, 30 b, 30 c and 30d. In the following this is characterized by the index s and indicatedby oblique shading. The test device 11 is to go on receiving busmessages 30 c, 30 f and 30 k, this being indicated by an index r and byvertical shading. The bus messages 30 c, 30 gf and 30 k to be receivedare for example transmitted by the bus subscribers 19. The further busmessage 30 e, transmitted by one of the bus subscribers 19, is of nointerest for the test device 11.

Admittedly the storage capacity 48 of the message memory 37 would besufficient for the bus messages 30 a, 30 b, 30 d, 30 g and 30 h of a busmessage sequence 47 as such. However in the message memory 37 memorycapacity received is to be reserved for the messages to be received sothat in all the storage capacity 48 is insufficient for all bus messages30 of the bus message sequence 47 to be transmitted.

The simulation and analysis module 28 transfers transmission data 65 forthe bus messages 30 a, 30 b, 30 d, 30 g and 30 h which are to betransmitted of the bus message sequence 47 to the test device 11. Therethe communication function 39 receives such bus message transmissiondata 65 and writes them as head data 54 a, 54 b, 54 d, 54 g and 54 htogether with user data 55 a, 55 b, 55 d, 55 g and 55 h associated withsuch head data to memory locations 49 of the intermediate memory 38. Thehead data 54 a and the user data 55 a serve for example for theproduction of the bus message 30 a.

The intermediate memory 38 has a substantially larger storage capacity50 than the message memory 37 of the bus controller 20, which only has asmaller storage capacity 48 for the storage of approximately six busmessages 30 to be transmitted and received. In the case of therepresentation of FIG. 4 in all eight of the memory locations 49 areillustrated for example. The intermediate memory 38 can for example bematrix-organized, one set of memory locations or slots S, which areavailable in the cycles C for the transmission and reception of busmessage 30 on the bus 12, constituting the lines and columns of suchmatrix. For example a FlexRay bus may have a maximum number of CN slots,such cycles being able to have a maximum number of SN slots. In the caseof the FlexRay bus for example 2,048 slots and 64 cycles are possible.It will be clear that the memory locations 49 are preferably dynamicallyorganized so that the storage capacity 50 is optimally utilized, Thepreceding writing of data for bus messages 30 from the intermediatememory 38 to the message memory 37 and vice versa in the oppositedirection the to the timely reading of received bus messages 30 from themessage memory 37 and transmission to the intermediate memory 38 takesplace in the following manner:

A head function 42, which constitutes a head preparing means, writes inadvance of a user data function 43 the head data 54 a, 54 b, 54 d, 54 gor 54 h of the respectively next bus messages to be transmitted from theintermediate memory 38 in a head data portion 51 of the message memory37 to one of the memory locations 56 r through 56 w.

A user data function 43, which constitutes a user data preparing means,writes the user data 55 a, 55 b, 55 d, 55 g and 55 h corresponding tothe head data 54 a, 54 b, 54 d, 54 g and 54 h, to user data memorylocations 57 r through 57 w of a user data part 52 of the message memory37.

For an locked phase 58 the bus controller 20 in the test device 11blocks bus messages 30 due for transmission. Accordingly the memorylocations 56 s, 56 t and 56 u for example are blocked for the busmessages 30 a and 30 b due for transmission and also the bus message 30c to be received at the transmission location or slot 34 c. The headdata memory locations 56 s, 56 t and 56 u are blocked for the headfunction 42. The head function 42 has however already offered the headdata 54 a and 54 b at the memory locations 56 s and 56 t. Even beforethe bus controller 20 has blocked the following head data memorylocation 56 v to avoid writing of data, the head function 42 writes thehead data 54 d to the memory location 56 v. The head function 42accordingly works in advance of the bus controller 20.

The user data function 43 is able to take its time for the writing ofdata to the user data portion 52. Admittedly the user data function 43may for example not modify the user data 55 a of the bus message 30 acurrently to be transmitted, because the bus controller 20 already needsthe user data 55 a stored there for forming the bus message 30 a andaccordingly appropriately blocks the memory location 57 u. The user data55 b on the other hand, which are associated with the bus message 30 b,can not be modified by the user data function 43. Accordingly it ispossible for, to take an example, the communication function 39 tomanipulate the user data 55 b in the intermediate memory 38 and for theuser data function 43 to modify them at short notice, and write the userdata 55 b to the message memory 37 at the memory location 57 t, whilethe bus controller 20 is already transmitting the bus message 30 a onthe bus 12. Accordingly the test device 10 can highly dynamicallytransmit bus messages 30 on the bus for simulation purposes.

Obviously the head function 42 and the user data function 43 may alterthe bus messages 30 to be transmitted further in the future in themessage memory 37 and for example write the head data 54 d and user data55 d to memory locations 56 v and 57 v. The memory location 57 v forexample contains user data 55 b′ as well from a preceding transmissioncycle 31′. The user data 43 overwrites the user data 55 b′ with the userdata 55 d.

The receiving function 41 also operates in advance of the bus controller20. Thus the receiving function 41 for example reads the memorylocations 56 w and 57 w in good time prior to rewriting by the buscontroller 20. At the memory locations 56 w and 57 w there are forexample user data 54 c′ and 55 c′ of a bus message 30′ of a transmissioncycle 31′ preceding the current transmission cycle 31. The receivingfunction 41 transfers the data of the bus message 30 c′ into theintermediate memory 38, whence they are read by the communicationfunction 39 and transferred to the simulation and analysis module 28.For this the intermediate memory 38 receives for this, for example, areception queue 66 and/or a reception queue 67 separate from theintermediate memory 38 is provided. The memory locations 56 w and 57 ware therefore already read by the receiving function 41, when the headfunction 42 and the user data function 43 write new head data 54 f anduser data 55 f of the current transmission cycle 32′ to these memorylocations.

There are still head data 54 d′ and 55 d′ of a bus message 34 d′ of thetransmission cycle 31′ at the memory locations 56 r and 57 r.

Pointers are directed to the user data memory location 57 r through 57 wamong the head data memory locations 56 r through 56 w, this beingindicated by the arrows 50.

The test device may also “force” the bus controller 20 to receive busmessages 30. When a bus controller 20 for example receives bus messageswithout a content, so-called zero or the like, it will not normallywrite, or will only do so partially, to the message memory 37. For busanalysis purposes however it may be appropriate also to receive zero orbus messages 30, which are to the discarded, and for example to issuethem with the aid of the simulation and analysis module 28.

The receiving function 41 marks for example the respective bus message30 c and 30 f to be “forcedly” received or, respectively, the portionsassociated with the associated slots 34 c and 35 f of the transmissioncycles 31 and 32 with a reception mark r, which signalizes that the busmessages 30 are to be received at the slots 34 c and 35 f in any case.For this purpose the receiving function 41 receives for example acontrol instruction 64 from the simulation and analysis module 28. Thusfor example at the head data memory locations 56 u and 56 w there is thereceived mark r. When the bus controller 20 writes the data of receivedbus messages, same will be read by the receiving function 41 and issuedto the control interface 27. When for example the user data of the busmessage 30 c′ do not contain any information, for example only zeroinformation, i. e. the bus message 30 c′ was a so-called zero frame, thereceiving function 41 preferably transmits a message 60 with a zero mark61 to the control interface 27.

Furthermore the test device 11 preferably acknowledges bus messages 30transmitted on the bus 12. The bus controller 20 for example marks busmessages transmitted on the bus 12 with a transmission mark 62. Thereceiving function 41 finds. on the basis of the transmission mark 62,that the respective bus message 30 has been transmitted on the bus 12,for example the bus message 30 d′ of the transmission cycle 31′ andfinds for the respectively transmitted bus messages 30, for example thebus messages 30 d′, an acknowledging message 63. The acknowledgingmessage 63 comprises data of the bus message 30 d′, and preferably theentire bus message 30 d′.

The communication function 39, the receiving function 41, the headfunction 42 and the user data function 43 are preferably designed asso-called engines, i. e. for example an update engine, an Rx engine,header engines and Ts engines. The functions 39, 41, 42 and 43preferably together take place cyclically one after the other, forexample using mutually consecutive calls, and an operating system (notillustrated), using a central control block or the like. Accordinglycollisions between the individual functions 39, 41, 42 and 43 areavoided so that for example the data in the intermediate memory 38 arealways consistent.

The bus controller 20 and the functions 39 and 41 through 43 are forexample components of a field programmable gate array (FPGA). It will beapparent that furthermore other designs are possible, for example assoftware implemented by a processor, or the like.

1. A test device for a motor vehicle bus, the test device comprising abus controller for the transmission and reception of bus messages, thebus controller having a message memory for offering transmission datafor bus messages, the message memory having a storage capacity for onebus message sequence with bus messages to be transmitted within a singletransmission cycle or a transmission cycle sequence, characterized inthat the test device comprises an intermediate memory for the storage oftransmission data for bus messages with a larger storage capacity thanthe message memory and that the test device comprises a transmissionpreparing means for reading the transmission data from the intermediatememory and for writing, preceding a reading of the bus controller, tothe message memory of the bus controller so that the bus messagesequence is expanded by additional bus messages, which are transmittedby the bus controller within the transmission cycle or the transmissioncycle sequence on the motor vehicle bus.
 2. The test device as set forthin claim 1, characterized in that the transmission preparing meanscomprise a head preparing means for writing head data to the messagememory and a user data preparing means for writing user data to themessage memory, the head data being provided for the production ofmessage heads of the bus message and the user data being provided forthe user data respectively following the message heads, of the busmessages, the head preparing means writing the message heads, before theuser data preparing means writes the associated user data to the messagememory, so that the user data preparing means can modify the user dataduring an locked phase, in which the bus controller in advance blocksthe writing of message heads to the message memory prior to thetransmission of a respective bus message.
 3. The test device as setforth in claim 1, characterized in that the storage capacity of themessage memory is provided for a maximum number of bus messagesdependent on a size of the bus messages.
 4. The test device as set forthin claim 1, characterized in that the bus is designed for time divisionmultiple access, and is more particularly a FlexRay bus.
 5. The testdevice as set forth in claim 1, characterized in that for the receptionof transmission data to be written to the intermediate memory itincludes a control interface for an operating means and moreparticularly a personal computer.
 6. The test device as set forth inclaim 1, characterized in that it is adapted for the transmission ofacknowledging messages by way of the control interface, theacknowledging messages acknowledging bus messages that are transmittedon the motor vehicle bus by the bus controller.
 7. The test device asset forth in claim 6, characterized in that the acknowledging messagescontain the content of the transmitted bus messages completely orpartially.
 8. The test device as set forth in claim 1, characterized inthat the bus controller is designed for writing bus messages of otherbus subscribers to the message memory which are transmitted by other bussubscribers between bus messages respectively to be transmitted by otherbus subscribers within or outside the bus message sequence.
 9. The testdevice as set forth in claim 1, characterized in that it includes areceiving means which gives the bus controller control instructions forthe reception of bus messages at predetermined transmission slots of themotor vehicle bus.
 10. The test device as set forth in claim 9,characterized in that the receiving means is adapted for writing areceived mark for transmission slots to the bus controller at which thebus controller is to receive bus messages.
 11. The test device as setforth in claim 10, characterized in that each memory location of themessage memory is associated with the transmission location of the motorvehicle bus and that the receiving means is adapted for marking memorylocations for respective bus messages to be received in the messagememory with the received mark, the bus controller writing the receivedbus messages to the memory locations provided with the mark.
 12. Thetest device as set forth in claim 10, characterized in that the buscontroller writes a zero mark or a zero information mark to memorylocations, if the memory location has a received mark associated with itand the bus controller has not received any bus message or a bus messagewith zero information to the respective transmission slot and that thereceiving means is adapted for the issue of the zero mark and the zeroinformation mark to the control interface.
 13. The test device as setforth in claim 5, characterized in that it is adapted for reading outreceived bus messages from the message memory and for the transfer ofthe received bus messages to the intermediate memory and/or the controlinterface, the test device reading a memory location containing areceived bus message of the message memory before rewriting by the buscontroller.
 14. The test device as set forth in claim 1, characterizedin that bus messages received in the message memory and to betransmitted are able to be stored.
 15. A test method for testing a motorvehicle bus comprising a test device having a bus controller for thetransmission and reception of bus messages, the bus controller having amessage memory for offering transmission data for bus messages, themessage memory having a message capacity for one bus message sequencewith bus messages to be transmitted within a single transmission cycleor a transmission cycle sequence characterized by the steps of: readingout transmission data for bus messages from an intermediate memoryhaving a larger storage capacity than the message memory, usingtransmission preparing means of the test device, writing, in advance ofthe reading by the bus controller, of the transmission data to themessage memory of the bus controller by the transmission preparing meansso that the bus message sequence is expanded by additional bus messages,which are transmitted by the bus controller (33) on the motor vehiclebus (12), and transmission of bus messages (30) on the basis of thetransmission data (65) prepared by the transmission data preparing means(40).